Abu Kharmeh Consulting Ltd

Microelectronics Design and Verification Engineering Services

Abu Kharmeh Consulting provides engineering services in microelectronics design and verification, specialising in digital design, RTL development and verification of complex ASIC/SoC systems using Verilog, VHDL and SystemVerilog. Its experience includes RTL design and verification, Ethernet protocol stacks and relevant IEEE standards, memory-related ASIC subsystems, low-power design and verification, and engineering automation. The company also applies AI-assisted engineering workflows, including agent skills and orchestration, to streamline day-to-day development. See the portfolio and members sections for more details.

ASIC Digital Design Consulting

Ericsson (Stockholm/Sweden - 2019)

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Digital Design and Verification Consulting

Intel Austria GmbH (Villach/Austria - 2016)

Implementation of 10G EPON Physical Coding Sublayer data path in VHDL
Synthesis and Static Timing Analysis (STA) using Intel Quartus
Performance optimization for mapping on FPGA for 10.3125Gbps traffic
Assertion based verification in VHDL
System modelling and verification in Verilog, SystemVerilog and UVM

Digital Design Verification Consulting

Renesas Electronics Europe GmbH (Dusseldorf/Germany - 2016)

Abstract specification of testbench architectures
Setting up mixed environments and testbenches (SVM, VMM and UVM)
Integration of VMM Verification IP into the verification flow
Implementation of test cases and functional covergroups in SystemVerilog

Digital Design and Verification Consulting

Intel Mobile and Communications GmbH (Dresden/Germany - 2014)

Setting up environment for power aware verification
Implementation and verification of design requirements in VHDL
Power aware methodology analysis and update of implementation accordingly
Using Synopsys Low Power Tools (VCS-NLP, DVE, Verdi)

Digital Design Verification Consulting

ST Microelectronics (Grenoble/France - 2012)

Specification of verification test-plan at sub-system level
Identification and addressing verification tools flow issues
Implementing low power verification API and test-plan
Debugging low-power tests using Synopsys tools (VCS-NLP)

Members

Suleiman Abu Kharmeh

PhD, Computer Architecture

Suleiman has a PhD in Computer Architecture and more than 14 years of experience in the semiconductor industry. His professional experience includes projects with Ericsson, Intel Labs Europe (ILE), NXP Semiconductors, Renesas Electronics, Intel Mobile Communications and STMicroelectronics. For more than seven years, he has contributed to memory-controller development as part of a team working on a large-scale ASIC, using both VHDL and SystemVerilog. His technical focus includes RTL design and subsystem/IP integration, Ethernet protocol stacks and relevant IEEE standards, simulation and debugging, and design-for-power work (dCGE) using Synopsys SpyGlass Power. His simulation and verification tool experience includes Cadence Xcelium, Synopsys VCS and VCS LP, as well as NCSIM. He also has experience with UPF, Design Compiler and Quartus. In day-to-day engineering, he makes extensive use of AI-assisted tools, particularly Kiro CLI, including custom skills and agent orchestration to automate and streamline development workflows. During his PhD, he was part of the Microelectronics Research Group, focusing on formalising the complexity and scalability of a communication-driven computer architecture for model-checking purposes. He is the founder and director of Abu Kharmeh Consulting Limited and continues research in formal hardware design and complexity analysis. Read More ...

Contact Details

3rd floor, 207 Regent Street
London W1B 3HH
United Kingdom

E: info@abukharmeh.com