Suleiman Abu Kharmeh

Profile

Suleiman has a PhD in Computer Architecture. He is currently working on a project with Ericsson in Stockholm/Sweden. He has also recently worked on projects with Intel Labs Europe (ILE) in Villach/Austria, NXP Semiconductors in Hamburg/Germany, Renesas Electronics Europe in Dusseldorf/Germany, Intel Mobile Communications in Dresden/Germany and STMicroelectronics in Grenoble/France. Currently he focuses on the specification, design and implementation of complex digital systems at the subsystem/IP integration level. Implementation is performed in VHDL, Verilog, SystemVerilog and UPF. Tools used are mainly NCSIM, VCS, DC, Spyglass and Quartus. During his PhD, he was part of the Microelectronics Research Group. The focus during his PhD was on formalising the complexity and scalability of a communication driven computer architecture for model-checking purposes. See his PhD thesis for more details. In addition to being the founder and director of Abu Kharmeh Consulting Limited, he is also continuing his research in the field of formal hardware design and complexity analysis. Full list of publications can be found here.

Personal info

Profesional Background Highlights

Ericsson

Stockholm, Sweden

Jan. 2019 - to date

ASIC Digital Design Consultant

Ongoing ...
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Intel Labs Europe (ILE)

Villach, Austria

Oct. 2016 - Dec. 2018

Digital Design Engineering Consultant

Implementation of 10G EPON Physical Coding Sublayer data path in VHDL
Synthesis and Static Timing Analysis (STA) using Intel Quartus
Performance optimization for mapping on FPGA for 10.3125Gbps traffic
Assertion based verification in VHDL
System modelling and verification in Verilog, SystemVerilog and UVM

Renesas Electronics Europe GmbH

Dusseldorf, Germany

Jan. 2016 - Jun. 2016

Digital Design Engineering Consultant

Abstract specification of testbench architectures
Setting up mixed environments and testbenches (SVM, VMM and UVM)
Integration of VMM Verification IP into the verification flow
Implementation of test cases and functional covergroups in SystemVerilog

Intel Mobile and Communications GmbH

Dresden, Germany

June 2014 - Nov. 2014

Digital Design Engineering Consultant

Setting up environment for power aware verification
Implementation and verification of design requirements in VHDL
Power aware methodology analysis and update of implementation accordingly
Using Synopsys Low Power Tools (VCS-NLP, DVE, Verdi)

ST Microelectronics

Grenoble, France

August 2012 - Dec. 2012

Digital Design Engineering Consultant

Specification of verification test-plan at sub-system level
Identification and addressing verification tools flow issues
Implementing low power verification API and test-plan
Debugging low-power tests using Synopsys Low Power Simulator (MVSIM/NLP)

Academic Background Highlights

University of Bristol

PhD in Microelectronics and Computer Engineering
Title: Formal Complexity-Oriented Performance-Critical Design and Verification Framework
Thesis date: Aug. 2012

University of Bristol

MSc with Distinction in Advanced Microelectronics Systems Engineering
Dissertation: Research and Implementation of Security Requirements of the XCore processor
Selected Subjects: Advanced Computer Architecture, Design Verification, System Integration, Digital System and Embedded Real Time Systems
Final GPA: 73.5%

An-Najah National University

Bachelor of Computer Engineering
Final GPA: High Good (86.5%)

Technical Skills

Design, Verification and Model-Checking

Languages and Methodologies: VHDL, Verilog, SystemVerilog, UVM, UPF, IP-XACT
Tools Knowledge: VCS, NCSIM, DC, Quartus and Specman e
Formal: CSPm and FDR3 modelling/model-checking

Embedded Control

Microcontroller system development (Altera's Nios II and Microchip's PIC)
Parallel embedded system design and development (XMOS's XC and MicroC/OS-II)

Other Languages

Bourne Shell, TCL, Make
Assembly Languages
XML, C/C++, Java

Revision Control

ClearCase
SVN
PerForce

Operating Systems

Linux
Windows

Technical Training

Advanced VHDL

Doulos Training Centre, Ringwood, UK.
December 2018

The course covers advanced use of VHDL for large hierarchical designs, design re-use, the creation of powerful test environment and gate level simulations.

Intermediate VHDL

FirstEDA Limited, Basingstoke, UK.
December 2017

The course gives practical experience in writing, testing and synthesing VHDL code as well as how to implement it on an FPGA. In addition, it enhances current understanding of VHDL through problematic hardware and FSM coding issues and techniques. Finally, it provides VHDL hardware experience with an FPGA lab board using industrial design and synthesis tools (Intel/Altera Quartus tool chain was used).

Universal Verification Methodology (UVM) Adopter Class

Doulos Training Centre, Ringwood, UK.
September 2015

The course leads delegates through to full verification project readiness by focussing on the in-depth practical application of UVM using industrial verification tools (Synopsys® VCS® was used on this occasion). Subjects covered include Functional Coverage, Random Stimulus Generation and UVM Code Generator among others.

Publications

Formal Complexity-Oriented Performance-Critical Design and Verification Framework

Suleiman Abu Kharmeh

This thesis develops a formal framework for the specification, complexity analysis and verification of functional and performance requirements of configurable communica- tion systems and protocols. The main objective is demonstrating the applicability of the proposed framework for the modelling and verification of a realistic system...

A Design-for-Verification Framework for a Configurable Performance-Critical Communication Interface

Suleiman Abu Kharmeh, Kerstin Eder, and David May

In this paper we present a Design-for-Verification framework for a Configurable Performance-Critical Communication Interface. To manage the inherent complexity of the problem we decomposed the interface into independent parametrisable communication blocks. Tock-CSP was then used to model the timing and functional specifications of our interface...

Formal Analysis of a Programmable Performance-Critical Processor Communication Interface

Suleiman Abu Kharmeh, Kerstin Eder, and David May

In this paper presents a Design-for-Verification approach applied to verify critical properties of a complex, programmable, performance-critical processor communication interface. The functional and performance requirements have been systematically decomposed into functionally independent communicating building blocks that can be individually...

Reconfigurable High-speed Asynchronous I/O Ports for Flexible Protocol Support

Suleiman Abu Kharmeh, and Simon Hollis

Many I/O protocols have elements in common, which may be exploited and shared between multiple on-chip protocol implementations, to yield area and energy savings. However, current implementations of I/O functionality in chips place each protocol in its own dedicated block, and so this potential advantage is never gained...

Research and Implementation of Security Requirements of the XCore Processor

Suleiman Abu Kharmeh

Masters Thesis

Design and Characterisation of a Wireless Inertial Measurement Unit for Integration to a Wireless Network Scenario

Andrew Lynch, Suleiman Abu Kharmeh, John Barton, Brendan O'Flynn, Philip Angove, and S C O Mathuna

This paper describes the design and characterisation of a Wireless Inertial Measurement Unit for deployment in a network. The IMU developed is an autonomous self-contained module purpose built for network integration. A software layer has been developed...

Selected Seminars

Dynamic Verification of Low Power Design Intent

Suleiman Abu Kharmeh and Francois Cerisier

Verification Futures Conference, Grenoble.
November 2012

Designs today include a complex set of power reduction techniques. These techniques are increasingly making their way from the system level down to lower level design entities including IP and block level of an electronic design...

A Design-for-Verification approach of a Configurable Performance-Critical Concurrent Communication Interface

Suleiman Abu Kharmeh

Department of Computer Science, University of Oxford
February 2011

We present a Design-for-Verification approach for a configurable performance-critical concurrent communication interface. To manage the inherent complexity of the problem we decomposed the interface...